1. Field of the Invention
This invention relates to processes for fabricating integrated circuits, especially those having both bipolar and field effect transistors. More particularly, the invention relates to a process for fabricating such circuits in which a sub-micron diffused bipolar emitter is formed in a strongly doped epitaxial layer.
2. Description of the Prior Art
Bipolar and field effect semiconductor (CMOS) technologies have each been independently understood for many years. The ability to combine complementary field effect devices ("CMOS") with bipolar devices on the same integrated circuit has raised new possibilities for very large scale integration. For example, bipolar output drivers may be employed with CMOS memories to provide more drive current. Because MOS circuits operate slower as temperature rises, while bipolar circuits operate faster, a CMOS bipolar combination ("BiCMOS") may be employed to make circuits less speed sensitive to temperature. Combining fast bipolar transistors with dense MOS transistors on the same integrated circuit permits the integration of complex functions with high yields. The CMOS transistors with their inherently low power requirements have large noise margins, while the bipolar devices have an advantage in switching speed and greater current drive per unit area.
Accordingly, much effort has been devoted by process scientists and engineers toward methods of integrating bipolar and CMOS processes on a single wafer. Unfortunately, to date the resulting BiCMOS processes generally are not optimized for either the CMOS or the bipolar aspect, consisting instead of a brute force combination of the process steps required to fabricate each type device. The result is often a lengthy and complicated process using a large number of masking operations, which is vulnerable to lower yields as a result of the complexity of the process. Typical prior art bipolar-CMOS processes are found in U.S. Pat. No. 4,484,388 to Iwasaki; U.S. Pat. No. 4,507,847 to Sullivan; and U.S. Pat. No. 4,536,945 to Gray et al. The use of aluminum isolation in integrated circuits is shown in Ramde et al., U.S. Pat. No. 4,512,816.